Download Analog Circuit Design: Low-Power Low-Voltage, Integrated by Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. PDF

By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)

The awareness of sign sampling and quantization at excessive pattern charges with low energy dissipation is a crucial objective in lots of purposes, includ­ ing transportable video units equivalent to camcorders, own verbal exchange units similar to instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic facts detection, etc. This paper describes structure and circuit methods for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive pace is taken to indicate sampling charges above 1 Mhz. within the first part the dif­ ferent conversion options acceptable during this variety of pattern premiums is dis­ stubborn. Following that the actual difficulties linked to energy minimization in video-rate pipeline ADCs is mentioned. those comprise optimi­ zation of capacitor sizes, layout of low-voltage transmission gates, and opti­ mization of switched capacitor achieve blocks and operational amplifiers for minimal energy dissipation. to illustrate of the appliance of those tech­ niques, the layout of a power-optimized lO-bit pipeline reduction converter (ADC) that achieves =1. sixty seven mW in keeping with MS/s of sampling cost from 1 MS/s to twenty MS/s is defined. 2. suggestions for CMOS Video-Rate reduction Conversion Analog-to-digital conversion recommendations should be categorised in lots of methods. One handy technique of evaluating ideas is to ascertain the variety of "analog clock cycles" required to supply one potent output pattern of the sign being quantized.

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Extra resources for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power

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If a difference occurs between this emitter voltage and VR the differential amplifier Q3J and Q32 feeds a correction signal to the output transistors. In this way the minimum current of the output transistors is controlled. Now suppose that the output stage is in rest. The voltages across R35 and R36 are equal and therefore the current. 135. is equally divided over Q34 and Q35. The emitter-voltage of Q35 and Q34 reflects the quiescent current of the output transistors. Again. if a difference occurs between this voltage and VR• the differential amplifier feeds a correction signal to the output transistors.

This dissipation is tied directly to the value of the sampling and DAC level generation capacitors that must be used in each stage of the pipeline, which in tum is dictated by fundamental kT/C considerations. The power dissipation required for dynamic switching of these capacitors during conversion is typically orders of magnitude lower than that actually dissipated by the operational amplifiers used. As a result, optimization of the design of the interstage gain block amplifiers is critically important for power reduction in the overall implementation.

2, April 1976, pp. 323-328. [9] E. Seevinck, W. de lager, P. Buitendijk, " A Low-Distortion Output Stage with improved stability for monolithic power amplifiers", IEEE I. Solid-State Circuits, Vol. SC-23, Iune 1988, pp. 794-801. H. Eschauzier, R. H. 246-247. M. E. , New York, 1988, pp. 690-701. H. S. Patent, Appl. No. 4,559,502, Dec. 17,1985. [13] I. H. Huijsing, "Operational Amplifier with I-V Rail-to-Rail MultipathDriven Output Stage", IEEE I. of Solid-State Circuits, vol. 26, No. 12, Dec. 1991, pp.

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