Download An Artificial Intelligence Approach to Integrated Circuit by Marwan A. Jabri PDF

By Marwan A. Jabri

In 1984, whereas i used to be following his postgraduate direction on VLSI layout, my manager Dr. David Skellern, requested me if i used to be attracted to investigating clever techniques to automated Ie floorplanning. He informed me then: "a circuit that works consistently appears to be like great, has a smart info and keep watch over movement. a quick approach to examine scholars' Ie initiatives is through taking a look at their fioorplans.". Later, I took a path on wisdom Engineering (KE) and synthetic Intelligence (AI) with Professor John Gero, who inspired me to enquire this sector of layout automation. The assets for such improvement have been fairly negative at IS&E as KE used to be a comparatively new box of study in Australia at the moment. \'Vhatever the problems (a strong programmmer by no means blames his instruments as David Skellern used to inform me), I undertook the research of Knowledge-Based techniques to Ie ftoor­ making plans as my PhD thesis topic with assistance from my manager and John Gero and the encouragement of all researchers at IS&E , who supplied a thrilling surroundings for my examine. This quantity experiences the result of my study in the course of 1984, 1985, 1986, and 1987. The voulme bargains with Ie ftoorplanning from 4 views: floorplanning approach, wisdom Engineering within the Ie area, the improvement of knowledge-based fioorplan­ ning approaches and new floorplanning algorithms to be used within the total strategy.

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Kozminski and Kinnen reported yet another algorithm for rectangular dualisation [35]. They reported a O( n 2 ) performance with their algorithm. Deas and Nixon proposed a system that considered specific circuits to have known floorplans [17]. The input graph to their system is searched for known patterns and clusters are created. Appropriate floorplanners are applied accordingly to each of the clusters. The pattern search involves complex graph processing algorithms. Examples of patterns are h-trees.

4 The Communication Solving Process Solving of the communication problem for a given hierarchical level of the circuit corresponds to the preparation of the circuit so it can be mapped into a rectangular topology where blocks map into rectangles and communicating blocks into adjacent rectangles. The region containing the external connections (I/O pads) is considered to represent an "exterior block" and is represented by the outside region of the rectangle enclosing the blocks of the circuit. As noted in the previous section, in a graph terminology, the communication solving involves the creation from the FBD graph of an RACG which admits an equivalent rectangular topology.

The basic reason behind this is the fact that bottom-up design offers much less freedom than top-down design, and therefore the number of elements on which we optimise is smaller. Block shape and port positions are two examples of attributes that are fixed and considered as input in a bottom-up approach, whereas they are considered as variables in a top-down methodology. Placement Automation Several algorithms have been proposed for automated placement, the most popular being based on Min-Cut techniques [30,9,37,58] and simulated annealing algorithms [31,60].

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